mirror of
https://github.com/Keychron/qmk_firmware.git
synced 2024-11-28 11:47:32 +06:00
172e6a7030
* Extensible split data sync capability through transactions. - Split common transport has been split up between the transport layer and data layer. - Split "transactions" model used, with convergence between I2C and serial data definitions. - Slave matrix "generation count" is used to determine if the full slave matrix needs to be retrieved. - Encoders get the same "generation count" treatment. - All other blocks of data are synchronised when a change is detected. - All transmissions have a globally-configurable deadline before a transmission is forced (`FORCED_SYNC_THROTTLE_MS`, default 100ms). - Added atomicity for all core-synced data, preventing partial updates - Added retries to AVR i2c_master's i2c_start, to minimise the number of failed transactions when interrupts are disabled on the slave due to atomicity checks. - Some keyboards have had slight modifications made in order to ensure that they still build due to firmware size restrictions. * Fixup LED_MATRIX compile. * Parameterise ERROR_DISCONNECT_COUNT.
198 lines
6.4 KiB
C
198 lines
6.4 KiB
C
/* Copyright 2021 QMK
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "serial_usart.h"
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#ifndef USE_GPIOV1
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// The default PAL alternate modes are used to signal that the pins are used for USART
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# ifndef SERIAL_USART_TX_PAL_MODE
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# define SERIAL_USART_TX_PAL_MODE 7
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# endif
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#endif
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#ifndef SERIAL_USART_DRIVER
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# define SERIAL_USART_DRIVER SD1
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#endif
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#ifdef SOFT_SERIAL_PIN
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# define SERIAL_USART_TX_PIN SOFT_SERIAL_PIN
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#endif
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static inline msg_t sdWriteHalfDuplex(SerialDriver* driver, uint8_t* data, uint8_t size) {
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msg_t ret = sdWrite(driver, data, size);
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// Half duplex requires us to read back the data we just wrote - just throw it away
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uint8_t dump[size];
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sdRead(driver, dump, size);
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return ret;
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}
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#undef sdWrite
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#define sdWrite sdWriteHalfDuplex
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static inline msg_t sdWriteTimeoutHalfDuplex(SerialDriver* driver, uint8_t* data, uint8_t size, uint32_t timeout) {
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msg_t ret = sdWriteTimeout(driver, data, size, timeout);
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// Half duplex requires us to read back the data we just wrote - just throw it away
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uint8_t dump[size];
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sdReadTimeout(driver, dump, size, timeout);
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return ret;
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}
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#undef sdWriteTimeout
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#define sdWriteTimeout sdWriteTimeoutHalfDuplex
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static inline void sdClear(SerialDriver* driver) {
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while (sdGetTimeout(driver, TIME_IMMEDIATE) != MSG_TIMEOUT) {
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// Do nothing with the data
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}
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}
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static SerialConfig sdcfg = {
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(SERIAL_USART_SPEED), // speed - mandatory
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(SERIAL_USART_CR1), // CR1
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(SERIAL_USART_CR2), // CR2
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(SERIAL_USART_CR3) // CR3
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};
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void handle_soft_serial_slave(void);
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/*
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* This thread runs on the slave and responds to transactions initiated
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* by the master
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*/
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static THD_WORKING_AREA(waSlaveThread, 2048);
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static THD_FUNCTION(SlaveThread, arg) {
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(void)arg;
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chRegSetThreadName("slave_transport");
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while (true) {
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handle_soft_serial_slave();
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}
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}
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__attribute__((weak)) void usart_init(void) {
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#if defined(USE_GPIOV1)
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palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
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#else
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palSetLineMode(SERIAL_USART_TX_PIN, PAL_MODE_ALTERNATE(SERIAL_USART_TX_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
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#endif
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#if defined(USART_REMAP)
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USART_REMAP;
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#endif
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}
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void usart_master_init(void) {
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usart_init();
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sdcfg.cr3 |= USART_CR3_HDSEL;
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sdStart(&SERIAL_USART_DRIVER, &sdcfg);
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}
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void usart_slave_init(void) {
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usart_init();
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sdcfg.cr3 |= USART_CR3_HDSEL;
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sdStart(&SERIAL_USART_DRIVER, &sdcfg);
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// Start transport thread
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chThdCreateStatic(waSlaveThread, sizeof(waSlaveThread), HIGHPRIO, SlaveThread, NULL);
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}
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void soft_serial_initiator_init(void) { usart_master_init(); }
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void soft_serial_target_init(void) { usart_slave_init(); }
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void handle_soft_serial_slave(void) {
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uint8_t sstd_index = sdGet(&SERIAL_USART_DRIVER); // first chunk is always transaction id
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split_transaction_desc_t* trans = &split_transaction_table[sstd_index];
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// Always write back the sstd_index as part of a basic handshake
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sstd_index ^= HANDSHAKE_MAGIC;
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sdWrite(&SERIAL_USART_DRIVER, &sstd_index, sizeof(sstd_index));
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if (trans->initiator2target_buffer_size) {
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sdRead(&SERIAL_USART_DRIVER, split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size);
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}
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// Allow any slave processing to occur
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if (trans->slave_callback) {
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trans->slave_callback(trans->initiator2target_buffer_size, split_trans_initiator2target_buffer(trans), trans->target2initiator_buffer_size, split_trans_target2initiator_buffer(trans));
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}
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if (trans->target2initiator_buffer_size) {
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sdWrite(&SERIAL_USART_DRIVER, split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size);
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}
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if (trans->status) {
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*trans->status = TRANSACTION_ACCEPTED;
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}
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}
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/////////
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// start transaction by initiator
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//
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// int soft_serial_transaction(int sstd_index)
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//
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// Returns:
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// TRANSACTION_END
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// TRANSACTION_NO_RESPONSE
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// TRANSACTION_DATA_ERROR
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int soft_serial_transaction(int index) {
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uint8_t sstd_index = index;
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if (sstd_index > NUM_TOTAL_TRANSACTIONS) return TRANSACTION_TYPE_ERROR;
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split_transaction_desc_t* trans = &split_transaction_table[sstd_index];
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msg_t res = 0;
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if (!trans->status) return TRANSACTION_TYPE_ERROR; // not registered
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sdClear(&SERIAL_USART_DRIVER);
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// First chunk is always transaction id
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sdWriteTimeout(&SERIAL_USART_DRIVER, &sstd_index, sizeof(sstd_index), TIME_MS2I(SERIAL_USART_TIMEOUT));
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uint8_t sstd_index_shake = 0xFF;
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// Which we always read back first so that we can error out correctly
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// - due to the half duplex limitations on return codes, we always have to read *something*
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// - without the read, write only transactions *always* succeed, even during the boot process where the slave is not ready
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res = sdReadTimeout(&SERIAL_USART_DRIVER, &sstd_index_shake, sizeof(sstd_index_shake), TIME_MS2I(SERIAL_USART_TIMEOUT));
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if (res < 0 || (sstd_index_shake != (sstd_index ^ HANDSHAKE_MAGIC))) {
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dprintf("serial::usart_shake NO_RESPONSE\n");
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return TRANSACTION_NO_RESPONSE;
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}
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if (trans->initiator2target_buffer_size) {
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res = sdWriteTimeout(&SERIAL_USART_DRIVER, split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size, TIME_MS2I(SERIAL_USART_TIMEOUT));
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if (res < 0) {
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dprintf("serial::usart_transmit NO_RESPONSE\n");
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return TRANSACTION_NO_RESPONSE;
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}
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}
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if (trans->target2initiator_buffer_size) {
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res = sdReadTimeout(&SERIAL_USART_DRIVER, split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size, TIME_MS2I(SERIAL_USART_TIMEOUT));
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if (res < 0) {
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dprintf("serial::usart_receive NO_RESPONSE\n");
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return TRANSACTION_NO_RESPONSE;
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}
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}
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return TRANSACTION_END;
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}
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