mirror of
https://github.com/Keychron/qmk_firmware.git
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931c7539d2
* Basic support for Maltron DQz11N1G controller replacement. * Update keyboards/handwired/dqz11n1g/rules.mk * Rehost images to cubeupload.com. (They were previously hosted via github wiki) * Apply suggestions from noroadsleft code review * Update keyboards/handwired/dqz11n1g/dqz11n1g.h
132 lines
3.7 KiB
C
132 lines
3.7 KiB
C
/*
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Copyright (c) 2022 David Kuehling <dvdkhlng TA posteo TOD de>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <avr/io.h>
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#include "spi_master.h"
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#include "quantum.h"
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#include "matrix.h"
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static pin_t row_pins[MATRIX_ROWS] = MATRIX_ROW_PINS;
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static void unselect_rows(void);
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void matrix_init_custom(void) {
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/* initialize row pins */
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for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
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setPinOutput(row_pins[row]);
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}
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unselect_rows();
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/* columns read via shift-register on SPI lines */
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/* Enable SPI, Master, set clock rate fck/2. First bit already at Qh
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* output before clock edge (CPHA=0). SN74HC165 shift register shifts
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* on low-to-high transition (CPOL=1). Receive the LSB first (DORD=1).
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*/
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bool lsbFirst = true;
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uint8_t mode = 2; /* CPOL=1, CPHA=0 */
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uint16_t divisor = 16;
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/* According to Atmega32U4 datasheet, PB0 *must* be set to output,
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* otherwise it will interfere with SPI master operation. On pro-micro
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* it's connected to a yellew LED. */
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pin_t slavePin = PB0;
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spi_init();
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spi_start(slavePin, lsbFirst, mode, divisor);
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/* Initialize pin controlling the shift register's SH/~LD pin */
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setPinOutput(ROW_SHIFT_PIN);
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}
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static void select_row(uint8_t row) {
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pin_t pin = row_pins[row];
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if (pin != NO_PIN) {
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writePinHigh(pin);
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}
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}
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static void unselect_row(uint8_t row) {
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pin_t pin = row_pins[row];
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if (pin != NO_PIN) {
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writePinLow(pin);
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}
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}
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static void unselect_rows(void) {
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for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
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unselect_row(row);
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}
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}
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bool matrix_read_cols_on_row(matrix_row_t current_matrix[], uint8_t current_row) {
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/* Start with a clear matrix row */
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matrix_row_t current_row_value = 0;
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/* Set shift register SH/~LD pin to "load" mode */
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writePinLow(ROW_SHIFT_PIN);
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select_row(current_row);
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matrix_output_select_delay();
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/* Set shift register SH/~LD pin to "shift" mode */
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writePinHigh(ROW_SHIFT_PIN);
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/* For each octet of columns... */
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for (uint8_t col_index = 0; col_index < MATRIX_COLS; col_index += 8) {
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spi_status_t read_result = spi_read();
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if (read_result >= 0) {
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/* only if SPI read successful: populate the matrix row with the
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state of the 8 consecutive column bits */
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current_row_value |= ((matrix_row_t)read_result << col_index);
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}
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}
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/* Unselect row & wait for all columns signals to go high. */
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unselect_row(current_row);
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matrix_output_unselect_delay(current_row, current_row_value != 0);
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/* Update row in matrix. */
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if (current_row_value != current_matrix[current_row]) {
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current_matrix[current_row] = current_row_value;
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return true;
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}
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return false;
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}
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bool matrix_scan_custom(matrix_row_t curr_matrix[]) {
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bool changed = false;
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/* set row, read cols */
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for (uint8_t current_row = 0; current_row < MATRIX_ROWS; current_row++) {
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changed |= matrix_read_cols_on_row(curr_matrix, current_row);
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}
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return changed;
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}
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/*
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* Local Variables:
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* c-basic-offset:4
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* fill-column: 76
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* End:
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*/
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