mirror of
https://github.com/Keychron/qmk_firmware.git
synced 2024-11-27 02:56:33 +06:00
172e6a7030
* Extensible split data sync capability through transactions. - Split common transport has been split up between the transport layer and data layer. - Split "transactions" model used, with convergence between I2C and serial data definitions. - Slave matrix "generation count" is used to determine if the full slave matrix needs to be retrieved. - Encoders get the same "generation count" treatment. - All other blocks of data are synchronised when a change is detected. - All transmissions have a globally-configurable deadline before a transmission is forced (`FORCED_SYNC_THROTTLE_MS`, default 100ms). - Added atomicity for all core-synced data, preventing partial updates - Added retries to AVR i2c_master's i2c_start, to minimise the number of failed transactions when interrupts are disabled on the slave due to atomicity checks. - Some keyboards have had slight modifications made in order to ensure that they still build due to firmware size restrictions. * Fixup LED_MATRIX compile. * Parameterise ERROR_DISCONNECT_COUNT.
242 lines
6.8 KiB
C
242 lines
6.8 KiB
C
/* Copyright (C) 2019 Elia Ritterbusch
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+
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <https://www.gnu.org/licenses/>.
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*/
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/* Library made by: g4lvanix
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* GitHub repository: https://github.com/g4lvanix/I2C-master-lib
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*/
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#include <avr/io.h>
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#include <util/twi.h>
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#include "i2c_master.h"
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#include "timer.h"
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#include "wait.h"
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#ifndef F_SCL
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# define F_SCL 400000UL // SCL frequency
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#endif
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#ifndef I2C_START_RETRY_COUNT
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# define I2C_START_RETRY_COUNT 20
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#endif // I2C_START_RETRY_COUNT
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#define TWBR_val (((F_CPU / F_SCL) - 16) / 2)
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#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
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void i2c_init(void) {
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TWSR = 0; /* no prescaler */
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TWBR = (uint8_t)TWBR_val;
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#ifdef __AVR_ATmega32A__
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// set pull-up resistors on I2C bus pins
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PORTC |= 0b11;
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// enable TWI (two-wire interface)
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TWCR |= (1 << TWEN);
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// enable TWI interrupt and slave address ACK
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TWCR |= (1 << TWIE);
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TWCR |= (1 << TWEA);
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#endif
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}
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static i2c_status_t i2c_start_impl(uint8_t address, uint16_t timeout) {
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// reset TWI control register
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TWCR = 0;
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// transmit START condition
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TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN);
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uint16_t timeout_timer = timer_read();
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while (!(TWCR & (1 << TWINT))) {
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if ((timeout != I2C_TIMEOUT_INFINITE) && ((timer_read() - timeout_timer) >= timeout)) {
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return I2C_STATUS_TIMEOUT;
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}
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}
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// check if the start condition was successfully transmitted
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if (((TW_STATUS & 0xF8) != TW_START) && ((TW_STATUS & 0xF8) != TW_REP_START)) {
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return I2C_STATUS_ERROR;
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}
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// load slave address into data register
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TWDR = address;
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// start transmission of address
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TWCR = (1 << TWINT) | (1 << TWEN);
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timeout_timer = timer_read();
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while (!(TWCR & (1 << TWINT))) {
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if ((timeout != I2C_TIMEOUT_INFINITE) && ((timer_read() - timeout_timer) >= timeout)) {
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return I2C_STATUS_TIMEOUT;
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}
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}
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// check if the device has acknowledged the READ / WRITE mode
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uint8_t twst = TW_STATUS & 0xF8;
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if ((twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK)) {
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return I2C_STATUS_ERROR;
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}
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return I2C_STATUS_SUCCESS;
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}
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i2c_status_t i2c_start(uint8_t address, uint16_t timeout) {
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// Retry i2c_start_impl a bunch times in case the remote side has interrupts disabled.
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uint16_t timeout_timer = timer_read();
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uint16_t time_slice = MAX(1, (timeout == (I2C_TIMEOUT_INFINITE)) ? 5 : (timeout / (I2C_START_RETRY_COUNT))); // if it's infinite, wait 1ms between attempts, otherwise split up the entire timeout into the number of retries
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i2c_status_t status;
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do {
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status = i2c_start_impl(address, time_slice);
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} while ((status < 0) && ((timeout == I2C_TIMEOUT_INFINITE) || (timer_elapsed(timeout_timer) < timeout)));
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return status;
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}
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i2c_status_t i2c_write(uint8_t data, uint16_t timeout) {
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// load data into data register
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TWDR = data;
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// start transmission of data
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TWCR = (1 << TWINT) | (1 << TWEN);
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uint16_t timeout_timer = timer_read();
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while (!(TWCR & (1 << TWINT))) {
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if ((timeout != I2C_TIMEOUT_INFINITE) && ((timer_read() - timeout_timer) >= timeout)) {
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return I2C_STATUS_TIMEOUT;
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}
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}
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if ((TW_STATUS & 0xF8) != TW_MT_DATA_ACK) {
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return I2C_STATUS_ERROR;
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}
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return I2C_STATUS_SUCCESS;
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}
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int16_t i2c_read_ack(uint16_t timeout) {
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// start TWI module and acknowledge data after reception
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TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWEA);
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uint16_t timeout_timer = timer_read();
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while (!(TWCR & (1 << TWINT))) {
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if ((timeout != I2C_TIMEOUT_INFINITE) && ((timer_read() - timeout_timer) >= timeout)) {
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return I2C_STATUS_TIMEOUT;
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}
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}
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// return received data from TWDR
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return TWDR;
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}
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int16_t i2c_read_nack(uint16_t timeout) {
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// start receiving without acknowledging reception
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TWCR = (1 << TWINT) | (1 << TWEN);
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uint16_t timeout_timer = timer_read();
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while (!(TWCR & (1 << TWINT))) {
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if ((timeout != I2C_TIMEOUT_INFINITE) && ((timer_read() - timeout_timer) >= timeout)) {
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return I2C_STATUS_TIMEOUT;
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}
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}
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// return received data from TWDR
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return TWDR;
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}
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i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_status_t status = i2c_start(address | I2C_WRITE, timeout);
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for (uint16_t i = 0; i < length && status >= 0; i++) {
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status = i2c_write(data[i], timeout);
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}
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i2c_stop();
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return status;
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}
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i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_status_t status = i2c_start(address | I2C_READ, timeout);
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for (uint16_t i = 0; i < (length - 1) && status >= 0; i++) {
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status = i2c_read_ack(timeout);
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if (status >= 0) {
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data[i] = status;
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}
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}
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if (status >= 0) {
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status = i2c_read_nack(timeout);
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if (status >= 0) {
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data[(length - 1)] = status;
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}
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}
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i2c_stop();
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return (status < 0) ? status : I2C_STATUS_SUCCESS;
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}
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i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_status_t status = i2c_start(devaddr | 0x00, timeout);
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if (status >= 0) {
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status = i2c_write(regaddr, timeout);
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for (uint16_t i = 0; i < length && status >= 0; i++) {
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status = i2c_write(data[i], timeout);
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}
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}
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i2c_stop();
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return status;
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}
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i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
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i2c_status_t status = i2c_start(devaddr, timeout);
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if (status < 0) {
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goto error;
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}
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status = i2c_write(regaddr, timeout);
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if (status < 0) {
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goto error;
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}
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status = i2c_start(devaddr | 0x01, timeout);
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for (uint16_t i = 0; i < (length - 1) && status >= 0; i++) {
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status = i2c_read_ack(timeout);
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if (status >= 0) {
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data[i] = status;
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}
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}
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if (status >= 0) {
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status = i2c_read_nack(timeout);
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if (status >= 0) {
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data[(length - 1)] = status;
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}
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}
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error:
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i2c_stop();
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return (status < 0) ? status : I2C_STATUS_SUCCESS;
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}
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void i2c_stop(void) {
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// transmit STOP condition
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TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);
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}
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