mirror of
https://github.com/Keychron/qmk_firmware.git
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74223c34a9
* `KC_RSHIFT` -> `KC_RSFT` * `KC_RCTRL` -> `KC_RCTL` * `KC_LSHIFT` -> `KC_LSFT` * `KC_LCTRL` -> `KC_LCTL`
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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Copyright 2012 Jun Wako <wakojun@gmail.com>
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Copyright 2016 Priyadi Iman Nurcahyo <priyadi@priyadi.net>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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/* matrix size */
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#define MATRIX_ROWS 17 // keycode bit: 3-0
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#define MATRIX_COLS 8 // keycode bit: 6-4
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/* legacy keymap support */
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#define USE_LEGACY_KEYMAP
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/* key combination for command */
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#define IS_COMMAND() ( \
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get_mods() == (MOD_BIT(KC_LSFT) | MOD_BIT(KC_RSFT) | MOD_BIT(KC_RALT) | MOD_BIT(KC_RCTL)) \
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)
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/*
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* PS/2 USART configuration for ATMega32U4
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*/
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#ifdef PS2_DRIVER_USART
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/* XCK for clock line */
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#define PS2_CLOCK_PIN D5
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#define PS2_DATA_PIN D2
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/* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
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/* set DDR of CLOCK as input to be slave */
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#define PS2_USART_INIT() do { \
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PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
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PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
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UCSR1C = ((1 << UMSEL10) | \
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(3 << UPM10) | \
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(0 << USBS1) | \
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(3 << UCSZ10) | \
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(0 << UCPOL1)); \
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UCSR1A = 0; \
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UBRR1H = 0; \
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UBRR1L = 0; \
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} while (0)
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#define PS2_USART_RX_INT_ON() do { \
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UCSR1B = ((1 << RXCIE1) | \
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(1 << RXEN1)); \
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} while (0)
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#define PS2_USART_RX_POLL_ON() do { \
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UCSR1B = (1 << RXEN1); \
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} while (0)
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#define PS2_USART_OFF() do { \
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UCSR1C = 0; \
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UCSR1B &= ~((1 << RXEN1) | \
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(1 << TXEN1)); \
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} while (0)
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#define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
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#define PS2_USART_RX_DATA UDR1
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#define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
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#define PS2_USART_RX_VECT USART1_RX_vect
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#endif
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/*
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* PS/2 Interrupt configuration
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*/
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#ifdef PS2_DRIVER_INTERRUPT
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/* uses INT1 for clock line(ATMega32U4) */
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#define PS2_CLOCK_PIN D1
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#define PS2_DATA_PIN D0
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#define PS2_INT_INIT() do { \
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EICRA |= ((1<<ISC11) | \
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(0<<ISC10)); \
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} while (0)
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#define PS2_INT_ON() do { \
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EIMSK |= (1<<INT1); \
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} while (0)
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#define PS2_INT_OFF() do { \
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EIMSK &= ~(1<<INT1); \
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} while (0)
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#define PS2_INT_VECT INT1_vect
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#endif
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/*
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* PS/2 Busywait configuration
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*/
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#ifdef PS2_DRIVER_BUSYWAIT
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#define PS2_CLOCK_PIN D1
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#define PS2_DATA_PIN D0
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#endif
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