output previous key state on TP1684 when scaning matrix.

This commit is contained in:
tmk 2010-11-06 01:58:47 +09:00
parent 89feab2301
commit 2ca3ab18a2
2 changed files with 31 additions and 14 deletions

View File

@ -84,7 +84,7 @@ Two PCBs are connected by 15 lines. Vcc and GND use 3 lines each, other 9 lines
2 Vcc(5V) 2 Vcc(5V)
3 Vcc(5V) 3 Vcc(5V)
4 TP1684 KEY: Low(0) when key pressed PE6 input(with pullup) 4 TP1684 KEY: Low(0) when key pressed PE6 input(with pullup)
5 TP1684 unknown:how to use PE7 input(with pullup) 5 TP1684 KEY_PREV: assert previous key state??? PE7 output
6 HC4051 A(bit0) select 8 rows(0 to 7) PB0 output 6 HC4051 A(bit0) select 8 rows(0 to 7) PB0 output
7 HC4051 B(bit1) PB1 output 7 HC4051 B(bit1) PB1 output
8 HC4051 C(bit2) PB2 output 8 HC4051 C(bit2) PB2 output
@ -148,9 +148,11 @@ Signals charts:
(HHKB_chart1.jpg) (HHKB_chart1.jpg)
Space bar locate at ROW:3 COL:7. Key are selected by HC4051(C,B,A) and LS145(C,B,A). Space bar locate at ROW:3 COL:7. A key is selected by HC4051(C,B,A) and LS145(C,B,A).
Key state can be read on TP1684(4/KEY) while asserting low on LS145(D). Key state can be read on TP1684(4/KEY) while asserting low on LS145(D).
Usage of TP1684(5) is unknown. Key state can be read without using this signal.
Usage of TP1684(5) is not clear. Controller seemed to output previous key state on this line.
However key state can be read without using this signal.
(HHKB_chart2.jpg) (HHKB_chart2.jpg)
@ -162,7 +164,13 @@ Matrix scan pseudo code:
for (col: 0-7) { for (col: 0-7) {
SELECT_COL(col); // set LS145(A,B,C) SELECT_COL(col); // set LS145(A,B,C)
_delay_us(50); _delay_us(40);
if (prev_key_state(row, col)) {
KEY_PREV_ON;
}
_delay_us(7);
ENALBLE_COL(); // set LS145(D) to low ENALBLE_COL(); // set LS145(D) to low
@ -174,6 +182,7 @@ Matrix scan pseudo code:
// not pressed // not pressed
} }
KEY_PREV_OFF;
UNALBLE_COL(); // set LS145(D) to high UNALBLE_COL(); // set LS145(D) to high
_delay_us(150); _delay_us(150);

View File

@ -19,13 +19,15 @@
// PB3, PB4, PB5, PB6(A, B, C, D) // PB3, PB4, PB5, PB6(A, B, C, D)
// use D as ENABLE: (enable: 0/unenable: 1) // use D as ENABLE: (enable: 0/unenable: 1)
// key: KEY: (on: 0/ off:1) // key: KEY: (on: 0/ off:1)
// UNKNOWN: unknown whether input or output // KEY_PREV: (on: 1/ off: 0)
// PE6,PE7(KEY, UNKNOWN) // PE6,PE7(KEY, KEY_PREV)
#define COL_ENABLE (1<<6) #define COL_ENABLE (1<<6)
#define KEY_SELELCT(ROW, COL) (PORTB = COL_ENABLE|(((COL)&0x07)<<3)|((ROW)&0x07)) #define KEY_SELELCT(ROW, COL) (PORTB = COL_ENABLE|(((COL)&0x07)<<3)|((ROW)&0x07))
#define KEY_ENABLE (PORTB &= ~COL_ENABLE) #define KEY_ENABLE (PORTB &= ~COL_ENABLE)
#define KEY_UNABLE (PORTB |= COL_ENABLE) #define KEY_UNABLE (PORTB |= COL_ENABLE)
#define KEY_ON ((PINE&(1<<6)) ? false : true) #define KEY_STATE (PINE&(1<<6))
#define KEY_PREV_ON (PORTE |= (1<<7))
#define KEY_PREV_OFF (PORTE &= ~(1<<7))
// matrix state buffer // matrix state buffer
static uint8_t *matrix; static uint8_t *matrix;
@ -52,9 +54,10 @@ void matrix_init(void)
// row & col output(PB0-6) // row & col output(PB0-6)
DDRB = 0xFF; DDRB = 0xFF;
PORTB = KEY_SELELCT(0, 0); PORTB = KEY_SELELCT(0, 0);
// KEY & VALID input with pullup(PE6,7) // KEY: input with pullup(PE6)
DDRE = 0x3F; // KEY_PREV: output(PE7)
PORTE = 0xC0; DDRE = 0xBF;
PORTE = 0x40;
// initialize matrix state: all keys off // initialize matrix state: all keys off
for (int i=0; i < MATRIX_ROWS; i++) _matrix0[i] = 0x00; for (int i=0; i < MATRIX_ROWS; i++) _matrix0[i] = 0x00;
@ -74,14 +77,19 @@ int matrix_scan(void)
for (int row = 0; row < MATRIX_ROWS; row++) { for (int row = 0; row < MATRIX_ROWS; row++) {
for (int col = 0; col < MATRIX_COLS; col++) { for (int col = 0; col < MATRIX_COLS; col++) {
KEY_SELELCT(row, col); KEY_SELELCT(row, col);
_delay_us(50); // from logic analyzer chart _delay_us(40); // from logic analyzer chart
if (matrix_prev[row] & (1<<col)) {
KEY_PREV_ON;
}
_delay_us(7); // from logic analyzer chart
KEY_ENABLE; KEY_ENABLE;
_delay_us(10); // from logic analyzer chart _delay_us(10); // from logic analyzer chart
if (KEY_ON) { if (KEY_STATE) {
matrix[row] |= (1<<col);
} else {
matrix[row] &= ~(1<<col); matrix[row] &= ~(1<<col);
} else {
matrix[row] |= (1<<col);
} }
KEY_PREV_OFF;
KEY_UNABLE; KEY_UNABLE;
_delay_us(150); // from logic analyzer chart _delay_us(150); // from logic analyzer chart
} }