2018-05-14 20:17:24 +06:00
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/* Library made by: g4lvanix
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* Github repository: https://github.com/g4lvanix/I2C-master-lib
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*/
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#include <avr/io.h>
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#include <util/twi.h>
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#include "i2c_master.h"
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#define F_SCL 400000UL // SCL frequency
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#define Prescaler 1
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#define TWBR_val ((((F_CPU / F_SCL) / Prescaler) - 16 ) / 2)
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void i2c_init(void)
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{
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2018-05-16 08:30:58 +06:00
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TWSR = 0; /* no prescaler */
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2018-05-14 20:17:24 +06:00
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TWBR = (uint8_t)TWBR_val;
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2018-05-16 08:30:58 +06:00
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//TWBR = 10;
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2018-05-14 20:17:24 +06:00
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}
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uint8_t i2c_start(uint8_t address)
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{
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// reset TWI control register
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2018-05-16 08:30:58 +06:00
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//TWCR = 0;
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// transmit START condition
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2018-05-14 20:17:24 +06:00
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TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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// check if the start condition was successfully transmitted
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2018-05-16 08:30:58 +06:00
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if(((TW_STATUS & 0xF8) != TW_START) && ((TW_STATUS & 0xF8) != TW_REP_START)){ return 1; }
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2018-05-14 20:17:24 +06:00
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// load slave address into data register
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TWDR = address;
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// start transmission of address
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TWCR = (1<<TWINT) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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// check if the device has acknowledged the READ / WRITE mode
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uint8_t twst = TW_STATUS & 0xF8;
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if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return 1;
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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return 0;
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}
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uint8_t i2c_write(uint8_t data)
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{
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// load data into data register
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TWDR = data;
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// start transmission of data
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TWCR = (1<<TWINT) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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2018-05-16 08:30:58 +06:00
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if( (TW_STATUS & 0xF8) != TW_MT_DATA_ACK ){ return 1; }
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2018-05-14 20:17:24 +06:00
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return 0;
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}
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uint8_t i2c_read_ack(void)
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{
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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// start TWI module and acknowledge data after reception
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2018-05-16 08:30:58 +06:00
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TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
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2018-05-14 20:17:24 +06:00
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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// return received data from TWDR
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return TWDR;
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}
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uint8_t i2c_read_nack(void)
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{
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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// start receiving without acknowledging reception
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TWCR = (1<<TWINT) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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// return received data from TWDR
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return TWDR;
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}
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uint8_t i2c_transmit(uint8_t address, uint8_t* data, uint16_t length)
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{
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if (i2c_start(address | I2C_WRITE)) return 1;
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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for (uint16_t i = 0; i < length; i++)
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{
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if (i2c_write(data[i])) return 1;
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}
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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i2c_stop();
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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return 0;
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}
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uint8_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length)
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{
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if (i2c_start(address | I2C_READ)) return 1;
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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for (uint16_t i = 0; i < (length-1); i++)
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{
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data[i] = i2c_read_ack();
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}
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data[(length-1)] = i2c_read_nack();
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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i2c_stop();
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2018-05-16 08:30:58 +06:00
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2018-05-14 20:17:24 +06:00
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return 0;
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}
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uint8_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length)
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{
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if (i2c_start(devaddr | 0x00)) return 1;
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i2c_write(regaddr);
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for (uint16_t i = 0; i < length; i++)
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{
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if (i2c_write(data[i])) return 1;
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}
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i2c_stop();
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return 0;
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}
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uint8_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length)
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{
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if (i2c_start(devaddr)) return 1;
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i2c_write(regaddr);
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if (i2c_start(devaddr | 0x01)) return 1;
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for (uint16_t i = 0; i < (length-1); i++)
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{
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data[i] = i2c_read_ack();
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}
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data[(length-1)] = i2c_read_nack();
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i2c_stop();
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return 0;
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}
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void i2c_stop(void)
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{
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// transmit STOP condition
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TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
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2018-05-16 08:30:58 +06:00
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// wait until stop condition is executed and bus released
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while(TWCR & (1<<TWSTO));
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2018-05-14 20:17:24 +06:00
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}
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