mirror of
https://github.com/Keychron/qmk_firmware.git
synced 2024-11-23 08:56:47 +06:00
3cf179be61
* adds proton c base * fixes custom matrix include * adds readme.md * initial proton coversion, no pin mapping * start of mcu selection * add pin mapping and sweet16 test * add at90 to list * disable backlight, fix d7 * update flag names * doc updates * proton c update for mcu selection
258 lines
9.5 KiB
C
258 lines
9.5 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F3xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F3xx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PREDIV_VALUE 1
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#define STM32_PLLMUL_VALUE 9
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
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#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
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#define STM32_USART1SW STM32_USART1SW_PCLK
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#define STM32_USART2SW STM32_USART2SW_PCLK
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#define STM32_USART3SW STM32_USART3SW_PCLK
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#define STM32_UART4SW STM32_UART4SW_PCLK
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#define STM32_UART5SW STM32_UART5SW_PCLK
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#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
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#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
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#define STM32_TIM1SW STM32_TIM1SW_PCLK2
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#define STM32_TIM8SW STM32_TIM8SW_PCLK2
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_USB_CLOCK_REQUIRED TRUE
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#undef STM32_HSE_BYPASS
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// #error "oh no"
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// #endif
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_DUAL_MODE FALSE
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#define STM32_ADC_COMPACT_SAMPLES FALSE
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_USE_ADC2 FALSE
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#define STM32_ADC_USE_ADC3 FALSE
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#define STM32_ADC_USE_ADC4 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC2_DMA_PRIORITY 2
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#define STM32_ADC_ADC4_DMA_PRIORITY 2
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#define STM32_ADC_ADC12_IRQ_PRIORITY 5
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#define STM32_ADC_ADC3_IRQ_PRIORITY 5
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#define STM32_ADC_ADC4_IRQ_PRIORITY 5
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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/*
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* CAN driver system settings.
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*/
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#define STM32_CAN_USE_CAN1 FALSE
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#define STM32_CAN_CAN1_IRQ_PRIORITY 11
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/*
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* DAC driver system settings.
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*/
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#define STM32_DAC_DUAL_MODE FALSE
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#define STM32_DAC_USE_DAC1_CH1 TRUE
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#define STM32_DAC_USE_DAC1_CH2 TRUE
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#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
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#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
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#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
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/*
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* EXT driver system settings.
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*/
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#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
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#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM6 TRUE
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#define STM32_GPT_USE_TIM7 TRUE
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#define STM32_GPT_USE_TIM8 TRUE
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#define STM32_GPT_TIM1_IRQ_PRIORITY 7
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#define STM32_GPT_TIM2_IRQ_PRIORITY 7
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#define STM32_GPT_TIM3_IRQ_PRIORITY 7
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#define STM32_GPT_TIM4_IRQ_PRIORITY 7
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#define STM32_GPT_TIM6_IRQ_PRIORITY 7
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#define STM32_GPT_TIM7_IRQ_PRIORITY 7
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#define STM32_GPT_TIM8_IRQ_PRIORITY 7
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 10
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#define STM32_I2C_I2C2_IRQ_PRIORITY 10
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#define STM32_I2C_USE_DMA TRUE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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#define STM32_ICU_TIM1_IRQ_PRIORITY 7
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#define STM32_ICU_TIM8_IRQ_PRIORITY 7
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_ADVANCED FALSE
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 TRUE
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#define STM32_PWM_USE_TIM3 TRUE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM8 FALSE
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#define STM32_PWM_TIM1_IRQ_PRIORITY 7
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#define STM32_PWM_TIM2_IRQ_PRIORITY 7
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#define STM32_PWM_TIM3_IRQ_PRIORITY 7
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#define STM32_PWM_TIM4_IRQ_PRIORITY 7
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#define STM32_PWM_TIM8_IRQ_PRIORITY 7
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_USART3 FALSE
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#define STM32_SERIAL_USE_UART4 FALSE
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#define STM32_SERIAL_USE_UART5 FALSE
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#define STM32_SERIAL_USART1_PRIORITY 12
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#define STM32_SERIAL_USART2_PRIORITY 12
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#define STM32_SERIAL_USART3_PRIORITY 12
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#define STM32_SERIAL_UART4_PRIORITY 12
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#define STM32_SERIAL_UART5_PRIORITY 12
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART3 FALSE
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_USB1 TRUE
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#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
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#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
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#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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#endif /* MCUCONF_H */
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