mirror of
https://github.com/Keychron/qmk_firmware.git
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104 lines
4.3 KiB
C
104 lines
4.3 KiB
C
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/*
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Copyright (C) 2020 Yaotian Feng, Codetector<codetector@codetector.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "hal.h"
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/* ============ Private Defines ===================== */
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/* ============ Function Prototypes ================== */
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#define PBIT(PORT, LINE) ((PAL_PORT(LINE) == PORT) ? (1 << PAL_PAD(LINE)) : 0)
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#define PAFIO_L(PORT, LINE, AF) (((PAL_PORT(LINE) == PORT) && (PAL_PAD(LINE) < 8)) ? (AF << (PAL_PAD(LINE) << 2)) : 0)
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#define PAFIO_H(PORT, LINE, AF) (((PAL_PORT(LINE) == PORT) && (PAL_PAD(LINE) >= 8)) ? (AF << ((PAL_PAD(LINE) - 8) << 2)) : 0)
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#define PAFIO(PORT, N, LINE, AF) ((N) ? PAFIO_H(PORT, LINE, AF) : PAFIO_L(PORT, LINE, AF))
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#define OUT_BITS(PORT) (PBIT(PORT, C2) | PBIT(PORT, C1) | PBIT(PORT, B5) | PBIT(PORT, B4) | PBIT(PORT, C3) | 0)
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#define IN_BITS(PORT) (PBIT(PORT, C4) | PBIT(PORT, C5) | PBIT(PORT, B10) | PBIT(PORT, B11) | PBIT(PORT, C0) | PBIT(PORT, A15) | PBIT(PORT, A8) | PBIT(PORT, A10) | PBIT(PORT, A11) | PBIT(PORT, A12) | PBIT(PORT, A13) | PBIT(PORT, A14) | PBIT(PORT, B2) | PBIT(PORT, B3) | 0)
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// Alternate Functions
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#define AF_BITS(PORT, N) (PAFIO(PORT, N, LINE_UART_RX, AFIO_USART) | PAFIO(PORT, N, LINE_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_TX, AFIO_USART) | PAFIO(PORT, N, LINE_BT_UART_RX, AFIO_USART) | PAFIO(PORT, N, C2, AFIO_GPIO) | PAFIO(PORT, N, C1, AFIO_GPIO) | PAFIO(PORT, N, B5, AFIO_GPIO) | PAFIO(PORT, N, B4, AFIO_GPIO) | PAFIO(PORT, N, C3, AFIO_GPIO) | PAFIO(PORT, N, C4, AFIO_GPIO) | PAFIO(PORT, N, C5, AFIO_GPIO) | PAFIO(PORT, N, B10, AFIO_GPIO) | PAFIO(PORT, N, B11, AFIO_GPIO) | PAFIO(PORT, N, C0, AFIO_GPIO) | PAFIO(PORT, N, A15, AFIO_GPIO) | PAFIO(PORT, N, A8, AFIO_GPIO) | PAFIO(PORT, N, A10, AFIO_GPIO) | PAFIO(PORT, N, A11, AFIO_GPIO) | PAFIO(PORT, N, A12, AFIO_GPIO) | PAFIO(PORT, N, A13, AFIO_GPIO) | PAFIO(PORT, N, A14, AFIO_GPIO) | PAFIO(PORT, N, B2, AFIO_GPIO) | PAFIO(PORT, N, B3, AFIO_GPIO) | 0)
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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const PALConfig pal_default_config = {
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// GPIO A
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.setup[0] =
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{
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.DIR = OUT_BITS(IOPORTA),
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.INE = IN_BITS(IOPORTA),
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.PU = IN_BITS(IOPORTA),
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.PD = 0x0000,
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.OD = 0x0000,
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.DRV = 0x0000,
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.LOCK = 0x0000,
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.OUT = 0x0000,
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.CFG[0] = AF_BITS(IOPORTA, 0),
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.CFG[1] = AF_BITS(IOPORTA, 1),
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},
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// GPIO B
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.setup[1] =
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{
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.DIR = OUT_BITS(IOPORTB),
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.INE = IN_BITS(IOPORTB),
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.PU = IN_BITS(IOPORTB),
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.PD = 0x0000,
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.OD = 0x0000,
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.DRV = 0x0000,
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.LOCK = 0x0000,
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.OUT = 0x0000,
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.CFG[0] = AF_BITS(IOPORTB, 0),
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.CFG[1] = AF_BITS(IOPORTB, 1),
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},
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// GPIO C
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.setup[2] =
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{
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.DIR = OUT_BITS(IOPORTC),
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.INE = IN_BITS(IOPORTC),
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.PU = IN_BITS(IOPORTC),
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.PD = 0x0000,
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.OD = 0x0000,
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.DRV = 0x0000,
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.LOCK = 0x0000,
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.OUT = 0x0000,
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.CFG[0] = AF_BITS(IOPORTC, 0),
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.CFG[1] = AF_BITS(IOPORTC, 1),
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},
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// GPIO D
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.setup[3] =
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{
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.DIR = OUT_BITS(IOPORTD),
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.INE = IN_BITS(IOPORTD),
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.PU = IN_BITS(IOPORTD),
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.PD = 0x0000,
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.OD = 0x0000,
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.DRV = 0x0000,
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.LOCK = 0x0000,
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.OUT = 0x0000,
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.CFG[0] = AF_BITS(IOPORTD, 0),
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.CFG[1] = AF_BITS(IOPORTD, 1),
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},
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.ESSR[0] = 0x00000000,
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.ESSR[1] = 0x00000000,
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};
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void __early_init(void) { ht32_clock_init(); }
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void boardInit(void) {}
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